NCR92C990 Ethernet/IEEE 802.3 Lan Controller Features - Register compatible with Am7990, rev. F - Supports the IEEE 802.3 standard for 10BASE5 type A, and 10BASE2 type B - Compatible with Am7992 Manchester Encoder/Decoder - Multiplexed address/data bus (16-bit data bus and 24-bit linear address) - Dual 48-byte internal FIFOs (one for transmit and one for receive) - Data byte swapping (8086/68000 microprocessors) - Programmable Address Latch Enable (ALE) - Supports DMA bus master and slave modes - Transmit/receive-based collision detection and recovery - Network and packet error reporting - Diagnostics - Internal/external loopback - CRC - Time Domain Reflectometry (TDR) - Submicron CMOS cell-based technology - ASIC macrocell core for customized designs - Available in a 68-pin PLCC Description The NCR92C990 is a Local Area Network (LAN) controller that supports IEEE 802.3 10BASE5 type A and 10BASE-T type B applications. The NCR92C990 provides a 16-bit interface for use in LAN adapter architectures and system buses. The NCR92C990 is suitable in both low-cost slave architectures and shared memory applications. The NCR(2C990 controls the network parameters of an IEEE 802.3 network and supports network management with network counters and status reports. Designed with NCR's cell-based technology, the NCR92C990's compatibility significantly reduces the difficulty in interfacing a microcomputer or minicomputer to an IEEE 802.3 Ethernet LAN. DMA and slave modes facilitate addressing to 24 bits. Bus master and slave modes are supported. The NCR92C990 has two independent, 48-byte FIFOs (one for transmit and one for receive). Network disgnostics and CRC error reporting are also supported. NCR offers EtherCore products that are sold as standard products for quick time-to-market designs. This family of EtherCore products is developed and supported by NCR's ASIC design tools. This allows designers to maintain control of cost/performance objectives and eliminate standard products that restrict design flexibility. Macrocell Pin Descriptions A(23:16) - High-Order Address Bits. During the bus master address segment of a memory transfer, these outputs contain the most significant eight bits of the 24-bit address. A_ENb is the enable for A(23:16). ADR - Register Address Port Select. This input selects which internal register is in use during a slave mode access. If ADR=1, the register address port is selected. ALEb_OUT - Address Latch Enable/Address Strobe This output demultiplexes the address bus. ALE is programmed through the ACON bit of Control/Status Register 3. BM0b_OUT and Bm1b_OUT - Byte Selection ------------------------------------ | BM0_OUT | BM1b_OUT | Mode | ------------------------------------ | 0 | 0 | 16-bit word | ------------------------------------ | 0 | 1 | upper byte | ------------------------------------ | 1 | 0 | lower byte | ------------------------------------ | 1 | 1 | not used | ------------------------------------ CSb - Chip Select. To select the NCR92C990 for slave access, drive this input low. CSb must remain active throughout the complete cycle. CLSN_IN - Collision. This input from the Manchester Encoder/Decoder (MENDEC) indicates a collision was detected. DAL_OUT(15:0) -- DAL_IN(15:0) -- Address/Data Line. During the address segment of a memory transfer, this split bus contains the lower 16 bits of memory address. During data read/write segments, this split bus contains 16 bits of data. DAL_ENb is the enable for DAL_OUT(15:0). DALIb_OUT -- External data bus transceiver control. This output is active in bus master mode only. It is asserted when DAL_OUT(15:0) is driven. DALIb_OUT=1 during a write cycle. DALIb_OUT=0 during a DATA segment of a read cycle. DALOb_OUT - External data bus transceiver control. This output is active in busmaster mode only. it is asserted when DAL_OUT(15:0) is driven. DALOb_OUT=0 during a write cycle and the ADDRESS segment of a read cycle. DASb_OUT - Data Strobe. This output identifies the data segment of the bus cycle. DASb_OUT=0 during the WRITE data segment of the bus master transfer. DASb_OUT=1 during the address segment of the bus master transfer. A low-to-high transition is used to latch WRITE data for a slave cycle. DASb_IN - Data Strobe. This input identifies the data segment of thebus cycle. DASb_IN=0 during the READ data segment of the bus master transfer. DASb_IN=1 during the address segment of the bus master transfer. A low-to-high transition is used to latch data READ. HLDAb - Hold Acknowledge When this input, HLDAb=0, in response to an assertion of HOLDb_IN, the NCR92C990 is the bus master. The controller waits for HLDAb to go high before reasserting HOLDb_OUT=0. HOLDb_OUT - Hold Request. The NCR92C990 asserts this active low output during memory accesses. It stays=0 for the entire burst. This pin is programmable through bit 0 of Control/Status Register 3. HOLDb_IN - Hold Request Sense. The NCR92C990 looks at HOLDb_IN input to sense the HOLDb condition. If HOLDb_IN=1 the NCR92C990 can drive HOLDb_OUT=0 to request the bus. INTRb_OUT - Interrupt. This active low output activates when any interrupts are generated according to the flags set in Control/Status Register 0. INTRb_OUT is disabled through bit 6 of Control/Status Register 0. (In which case INTRb_OUT will remain high.) RCLK_IN - Receive Closk. This input is the 10 MHz receive clock from the MENDEC. READ_IN - Read Data In. This input is used to define the read/write operation. For a slave cycle READ_IN=0 to output data (write). READ_IN=1 to input data (read). ------------------------------------- | Cycle | READ_IN | Type | ------------------------------------- | | 0 | Data output | | Slave |-----------|-------------| | | 1 | Data input | ------------------------------------- READ_OUT - Read Data Out. This output is used to define the read/write operation. For a master cycle READ_OUT=1 to input data (read), READ_OUT=0 to output data (write). ------------------------------------- | Cycle | READ_OUT | Type | ------------------------------------- | Bus | 1 | Data output | | Master |-----------|-------------| | | 0 | Data input | ------------------------------------- READYb_IN - Ready (Master mode). This active low input in a bus master mode is used to provide an asynchronous acknowledgement that a transfer can be performed. The READ_OUT signal determines whether a read or write transfer is taking place. READYb_OUT - Ready (Slave mode). Asserted active low output is generated in response to DASb_IN for a Slave read or write. The READ_IN signal determines whether a read or write transfer is taking place. RENA_IN - Receive Enable. This buffered input from the MENDEC signifies a carrier present. RESETb - Reset. This active low buffered input is a system reset for the NCR92C990 macrocell. RX_IN - Receive Data. This is the buffered receive data input from the MENDEC data output. TBUS(17:0) - Test Bus Outputs. These outputs are used for testing and are always driven. TCLK - Transmit Clock. This buffered input is the system clock from the MENDEC. TENA_OUT - Transmitter Enable. This is an output to the MENDEC to enable the MENDEC transmitter. TESTb - Test Mode Enable. This active low input is driven low to enable the NCR92C990 internal test features. TESTb should be driven high for normal operation. TESTRb - Test Mode Enable. This active low input is driven low to enable the NCR92C990 internal test features. TESTRb should be driven high for normal operation. TX_OUT - Transmit Data. This output is the transmit data to the MENDEC. Functional Description Bus Interface The NCR92C990 is designed to be compatible with a variety of microprocessors. Internal logic for byte swapping enables different bus organizations to be supported. The programmable Address Latch Enable (ALE) output supports interfaces with different microprocessors and it is register programmable. The bus master mode supports 24-bit DMA with addressing and 16-bit programmable data byte addressing. Bus Master Mode Data is transferred to and from the NCR92C990 through DMA transfers. The data transfers are timed by using ALEb_OUT, DASb_IN, DASb_OUT, READYb_IN and READYb_OUT. Slave Mode The slave mode is active when the host asserts the CSb input and initiates a read or write to a register or to the register address port. Lan Interface The NCR92C990 supports error reporting for diagnostics, addressing, collision, babbling transmitter (jabbering), packet framing, overflow and underflow. Diagnostic Modes Internal and external loopback modes are supported by the NCR92C990; they are configured through the internal registers. Addressing Modes Physical, logical and promiscuous modes are supported. Physical: Packets can be received that have the full 48-bit destination address matching the physical address that is programmed into the NCR92C990 during initialization. Logical: Packets can be received only if the destination address matches one of 64 logical addresses programmed in the logical address filter at initialization. Promiscuous: A promiscuous mode allows reception of all packets. All incoming, error-free packets are accepted and stored in the buffer memory regardless of destination address or length. Collision Detection The NCR92C990 supports collision detection and recovery for both transmit and receive functions. Transmitting: Upon a collision during transmit, the NCR92C990 will jam with 1 bit for 32 bit times and then back off for a multiple number of slot-times. A slot-time is equal to 512 bit-times @ 10 MHz/100 ns periods. The delay for the next transmission is chosen from a uniformly distributed random integer in the range of 1 to 2^k where k=1,2,3,...n. Collisions during preamble, destination or source address fields, data fields, and CRC are handles in the same manner. Receiving: Upon a collision during receive, the packet reception terminates immediately. A collision that occurs before the 64-byte interval results in a runt packet. A collision that occurs after the 64-byte interval causes a truncated packet that is transferred to memory. A CRC error is reported in this case. Descriptor Ring Management Buffer management for the NCR92C990 is handled by a recurrent list of assignments in memory called descriptor rings. There are separate descriptor rings for both transmit and receive. The NCR92C990 searches the descriptor rings for both transmit and receive. The NCR92C990 searches the descriptor rings to determine the next empty buffer. After an empty buffer is filled, the OWN bit is set in that descriptor ring. When a descriptor ring has its OWN bit set, the NCR92C990 starts a DMA transfer using the descriptor ring buffer pointer which points to the data memory buffer. Internal Registers Initialization Block The NCR92C990 reads a data structure in memory to initialize pointers to memory transmit and receive buffers. This sets the mode of operation, and reads the logical address filter programming as well as the controllers physical address on the network. The initialization data structure contains the following: - Mode Register - Physical address - Logical address filter - Receive ring address pointer and length - Transmit ring address pointer and length Mode Register 15 6 5 4 3 2 1 0 ------------------------------------------------- | PRO | ILB | DRY | COL | DTC | LBK | DTX | DRX | ------------------------------------------------- ------------------------------------------------------------------------ | Bits | Name | Description | ------------------------------------------------------------------------ | 0 | DRX | Disable Receiver. When this bit is set, the NCR92C990 | | | | rejects all incoming packets because the receive | | | | descriptor ring isnot accessed. DRX=1 will clear the | | | | RON bit in the Control/Status Register 0 when | | | | initialization is done. | ------------------------------------------------------------------------ | 1 | DTX | Disable Transmitter. When this bit is set, the | | | | NCR92C990 does not access the transmit descriptor ring | | | | so no transmissions are attempted. DTX=1 will clear | | | | the TON bit in Control/Status Register 0 when | | | | initialization is done. | ------------------------------------------------------------------------ | 2 | LBK | Loopback. Loopback allows the NCR92C990 to transmit a | | | | packet addressed to itself which can be used to test | | | | the LAN interface at various levels. The packet size | | | | is limited to 8-32 bytes with 4 bytes allowed for CRC | | | | when DTC=0. Runt packet detection is disabled. TBK=1 | | | | allows concurrent transmit and receive for a packet | | | | length constrained to fit in the SILO. Transmission | | | | will begin when the entire packet is in the SILO. The | | | | entire received packet will be written to memory only | | | | after reception is complete. Transmit data chaining | | | | is not allowed if the receive packet length does not | | | | exceed 32 bytes. | ------------------------------------------------------------------------ | 3 | DTC | Disable Transmit CRC. When DTC=0, the transmitter gen-| | | | erates and appends CRC to the transmitted packet. When | | | | DTC=1, no CRC is appended to the packet. During LBK | | | | mode, DTC=1 will cause CRC to be appended to the trans-| | | | mitted packet. Receive CRC will be checked by the | | | | NCR92C990 and written into memory. DTC=1 disables CRC | | | | append during transmit. The host must append the CRC | | | | to the transmit packet in this case. Receive CRC will | | | | be checked. | ------------------------------------------------------------------------ | 4 | COL | Force Collision. This bit allows testing of the | | | | collision logic. The NCR92C990 must be in internal | | | | loopback mode for COL to be valid. If COL=1, a | | | | collision will be forced during the next transmit and | | | | can result in 16 transmission retries. Transmit | | | | Descriptor 3 RTY will be set = 1 in this case. | ------------------------------------------------------------------------ | 5 | DRY | Disable Retry. When DRY=1, the NCR92C990 attempts to | | | | transmit a packet only once. If there is a collision | | | | on this first attempt, a retry error is reported. In | | | | Transmit Descriptor 3, RTY=1. | ------------------------------------------------------------------------ | 6 | ILB | Internal Loopback. This is set when the LBK bit to | | | | determine where the loopback function is done. The | | | | NCR92C990 does not receive any external packets when it| | | | is in internal loopback mode. The packet size is | | | | limited to 8-32 bytes. Extend packet reception is | | | | disabled. Multicast addressing in External Loopback | | | | (LBK) is valid only when DTC=1. Received packets will | | | | be accepted from the network. ILB is valid only when | | | | LBK=1. | ------------------------------------------------------------------------ ---------------------------------------- | LBK | ILB | Loopback Mode | ---------------------------------------- | 0 | X | Normal mode | ---------------------------------------- | 1 | 0 | External Loopback | ---------------------------------------- | 1 | 1 | Internal Loopback | ---------------------------------------- ------------------------------------------------------------------------ | Bits | Name | Description | ------------------------------------------------------------------------ | 14-7 | res | Reserved. | ------------------------------------------------------------------------ | 15 | PRO | Promiscuous mode. When PRO=1, all incoming packets | | | | are accepted. | ------------------------------------------------------------------------ Physical Address (PADR) The physical address is the unique 48-bit physical address assigned to the NCR92C990. PADR(0) must = 0. Logical Address Filter (LADR) The logical address filter is a 64-bit mask used by the NCR92C990 to accept logical addresses. It is composed of four 16-bit registers. The logical address filter is a 64-bit mask used to qualify incoming packets. After the 48 bits of the destination address have gone through the LADR CRC circuit, the high order 6 bits of the 32 bit LADR CRC value are set to select 1 of 64 bit positions in the Logical Address filter. If a bit posibion in the logical address filter = 1, the packet will be accepted. Broadcast address (all ones) pass transparently through thelogical address filter. If the logical address filter (LADR)=0, all packets are rejected except Broadcast packets. Receive Ring Pointer 31-29 28-24 23-3 2 1 0 ---------------------------------------------------- | RRL | res | RRA | zero | zero | zero | ---------------------------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 2-0 | zero | These bits must be zero. Receive Ring Pointers are | | | | quad word boundary aligned. | ---------------------------------------------------------------------- |23-3 | RRA | Receive Ring Address. These bits are the lowest | | | | address bits of the receive ring. | ---------------------------------------------------------------------- |28-24 | res | These bits are reserved for internal use. | ---------------------------------------------------------------------- |31-29 | RRL | Receive Ring Length. This is the number of entries | | | | in the receive ring expressed as a power of two. | ---------------------------------------------------------------------- ---------------------------------------- | RRL | Number of Entries | ---------------------------------------- | 0 | 1 | ---------------------------------------- | 1 | 2 | --------------------------------------- | 2 | 4 | ---------------------------------------- | 3 | 8 | ---------------------------------------- | 4 | 16 | ---------------------------------------- | 5 | 32 | ---------------------------------------- | 6 | 64 | ---------------------------------------- | 7 | 128 | ---------------------------------------- Transmit Ring Pointer 31-29 28-24 23-3 2 1 0 ---------------------------------------- | TRL | res | TRA | zero | zero | zero | ---------------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 2-0 | zero | These bits must be zero. Transmit Rings are aligned | | | | with quad word boundaries. | ---------------------------------------------------------------------- | 23-3 | TRA | Transmit Ring Address. These bits are the lowest | | | | address bits of the transmit ring. | ---------------------------------------------------------------------- | 28-24| res | These bits are reserved for internal use. | ---------------------------------------------------------------------- | 31-29| TRL | Transmit Ring Length. This is the number of entries | | | | in the transmit ring expressed as a power of two. | ---------------------------------------------------------------------- --------------------------- | TRL | Number of Entries | --------------------------- | 0 | 1 | --------------------------- | 1 | 2 | --------------------------- | 2 | 4 | --------------------------- | 3 | 8 | --------------------------- | 4 | 16 | --------------------------- | 5 | 32 | --------------------------- | 6 | 64 | --------------------------- | 7 | 128 | --------------------------- COntrol/Status Registers The Control/Status registers are accessed through the register address port and the register data port. The status register being accessed is determined by the value of the ADR input. When ADR=0, the register data port is selected and when ADR=1, the register address port is selected. The address of the Control/Status register to be accessed is written to the register address port. All subsequent reads and writes to the data port have the same data read/written to the selected Control/Status register. Register Address Port 15 2 1 0 ---------------------------------------------- | res | C/S REG1 | C/S REG0 | ---------------------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 1-0 | C/S | Control/Status Register Select. The Register Address| | | | Port is READ/WRITE and selects the Control/Status | | | | Register to be accessed through the Register Data | | | | Port. RESETb clears the Register Address Port. | ---------------------------------------------------------------------- | 15-2 | res | Reserved. Read as 0. | ---------------------------------------------------------------------- --------------------------------------------- | Bit 1 | Bit 0 | Register | --------------------------------------------- | 0 | 0 | Control/Status Register 0 | --------------------------------------------- | 0 | 1 | Control/Status Register 1 | --------------------------------------------- | 1 | 0 | Control/Status Register 2 | --------------------------------------------- | 1 | 1 | Control/Status Register 3 | --------------------------------------------- Register Data Port 15 0 ---------------------------------------- | DATA | ---------------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 15-0 | DATA | Data written to the Register Data Port is actually | | | | written to the Control/Status register selected by | | | | the Register Address Port. The Control/Status | | | | Registers 1, 2, and 3 are only accessible when the | | | | stop bit is set in Control/Status Register 0. | ---------------------------------------------------------------------- Control Stauts Register 0 15 14 13 12 11 10 9 8 7 6 5 --------------------------------------------------------------------- | ERR | BAB | CE | MISS | ME | RINT | TINT | IFIN | INT | IEN | RON | --------------------------------------------------------------------- 4 3 2 1 0 ------------------------------- | TON | TD | STP | STR | INIT | ------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 0 | INIT | Initialize. This bit causes the NCR92C990 to start | | | | the initialization procedure and access the | | | | initialization block. Set the STP bit prior to | | | | setting INIT. INIT clears the STP bit. INIT is | | | | Read/Write with a 1 only. Writing zero bits into | | | | INIT has no effect. INIT is cleared by chip reset on| | | | setting STP. | ---------------------------------------------------------------------- | 1 | STR | Start. Start enables the NCR92C990 to send and | | | | receive packets, access memory, and perform | | | | management tasks. Set the STP bit prior to setting | | | | STR. INIT clears the STR bit. Wait until IFIN=1 | | | | to set STR. STR is Read/Write with a 1 only. STR is | | | | cleared by reset. | ---------------------------------------------------------------------- | 2 | STP | Stop. STP disables the NCR92C990 from all external | | | | activity when set and clears the internal logic. STP| | | | is the same as RESETb. STP stays set until STR or | | | | INIT is set. STP is Read/Write with a 1 only. STP | | | | is set by RESETb. STP is cleared by INIT or STR. | ---------------------------------------------------------------------- | 3 | TD | Transmit Demand. This bit causes the NCR92C990 to | | | | access the Transmit Ring Pointer register without | | | | waiting for a time interval. TD is write with 1 only.| | | | TD is cleared by RESETb or by STP=1. | ---------------------------------------------------------------------- | 4 | TON | Transmitter On. This bit shows that the transmitter | | | | is enabled. TON is cleared by RESETb or by setting | | | | STP. TON is set=1 when STR=1 and DTX=0 in the Mode | | | | Register, for example, initialization block has been | | | | read. TON is Read only. TON is cleared by RESETb | | | | or STP=1. | ---------------------------------------------------------------------- | 5 | RON | Receiver On. This bit shows that the receiver is | | | | enabled. RON is cleared by RESETb or by setting STP | | | | RON is set = 1 when STR = 1 and DRX = 0 in the Mode | | | | Register for example, initialization block has been | | | | read. RON is cleared by Minor Error (ME), or, if | | | | IFIN=1 from setting INIT=1 and DRX=1 in the Mode | | | | Register. RON is Read only and is cleared by RESETb | | | | or STP=1. | ---------------------------------------------------------------------- | 6 | IEN | Interrupt Enable. IEN allows the INT bit to go low. | | | | IEN cannot be set while STP is set, but it can be | | | | set in parallel or afterwards. If IEN=1 and INT=1, | | | | the INTRb_OUT pin will = 0. Otherwise INTRb_OUT=1. | | | | IEN is Read/Write and is cleared by RESETb or STP=1. | ---------------------------------------------------------------------- | 7 | INT | Interrupt. INT is set by any of the following bits | | | | being set: BAB, MISS, ME, RINT, TINT, and IFIN. INT | | | | is Read only and is cleared by RESETb or by clearing | | | | the interrupt cause. | ---------------------------------------------------------------------- | 8 | IFIN | Initialization Finished. This bit indicates that the| | | | NCR92C990 has finished the initialization procedure | | | | started by the INIT bit. All new parameters in the | | | | initialization block are now stored. When IFIN=1, an| | | | interrupt is generated if IEN=1. IFIN is Read/Clear | | | | and is cleared by writing a 1 to IFIN. RESETb and | | | | STP=1 clear IFIN. | ---------------------------------------------------------------------- | 9 | TINT | Transmitter Interrupt. This bit is set when the | | | | NCR92C990 updates an entry in the transmit ring | | | | description for the last buffer sent or if a | | | | receive is stopped due to an error. When TINT=1 | | | | an interrupt is generated if IEN=1. | ---------------------------------------------------------------------- | 10 | RINT | Receiver Interrupt. This bit is set when the | | | | NCR92C990 updates an entry in the receive ring | | | | description for the last buffer received or if a | | | | receive is stopped due to an error. When RINT=1, | | | | an interrupt is generates if IEN=1. | ---------------------------------------------------------------------- | 11 | ME | Memory Error. This bit is set when the NCR92C990 | | | | is in bus master mode and has not receiver a signal | | | | from READYb_IN after asserting the address on | | | | DAL_OUT(15:0). READYb_IN must be received within | | | | 102.4 microseconds after asserting DAL_OUT(15:0). | | | | The Receiver and Transmitter are turned off if ME=1, | | | | and if IEN=1 an interrupt is generated. ME is Read/ | | | | Clear by writing a 1 to ME. RESETb or STP=1 clear | | | | ME. | ---------------------------------------------------------------------- | 12 | MISS | Missed Packet. This bit is set when the receiver | | | | loses a packet of data because it does not own any | | | | receive buffer. An interrupt is generated if IEN=1. | | | | If MISS=1 and IEN=1, an interrupt is generated. MISS | | | | is Read/Clear by writing a 1 to MISS. RESETb on | | | | STP=1 clears MISS. | ---------------------------------------------------------------------- | 13 | SQE | Signal Quality Error test. This bit is set when the | | | | SQE test that follows every packet transmission fails| | | | This indicated that the collision detection circuitry| | | | in the transceiver may be faulty. Packets still | | | | transmit, but should be retransmitted because they | | | | may have collided without the collision being | | | | detected. SQE=1 means that on transmission the CLSN | | | | pin started to activate within 2.2 microseconds after| | | | the fall of RENA. | ---------------------------------------------------------------------- | 14 | BAB | Babble. This bit shows a transmitter time-out error.| | | | It indicates that the transmitter has been on the | | | | channel longer than the time required to send the | | | | maximum length packet. BAB will be set after 1519 | | | | bytes have been transmitted. If IEN=1, an interrupt | | | | will be generated. BAB is Read/Clear by writing a 1 | | | | to BAB. BAB is cleared by RESETb or STP=1. | ---------------------------------------------------------------------- | 15 | ERR | Error. ERR is set by any of the following bits being| | | | set: BAB, SQE, MISS, and ME. ERR stays set while any| | | | of these errors are true. ERR is cleared by RESETb, | | | | by setting STP, or by clearing the individual error. | | | | ERR is Read only. | ---------------------------------------------------------------------- Control/Status Register 1 Accessible only when STP=1 and RAP=1. Contents are best after STP=1. 15 1 0 ---------------------------------------- | DAL_IN(15:1) | zero | ---------------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 0 | zero | This bit must be set to zero. | ---------------------------------------------------------------------- | 15-1 | DAL | These 15 bits, along with 0, are the low order 16 | | | | bits of the initialization block address. | ---------------------------------------------------------------------- Control/Status Register 2 Accessible only when STP=1 and RAP=2. Contents are best after STP=1. 15 8 7 0 ------------------------------- | res | A(23:16) | ------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 7-0 | A(23:16) | This represents the high order 8 bits of the | | | | initialization block address. | ---------------------------------------------------------------------- | 15-8 | res | Reserved. | ---------------------------------------------------------------------- Control/Status Register 3 Accessible only when STP=1 and RAP=3. Contents are lost after STP=1. CSR3 is cleared by RESETb or STP=1. 15 14 12 11 9 8 3 2 1 0 --------------------------------------------------- | IPGS | RX-TX | TX-TX | res | SWAP | ACON | BCON | | | IPG | IPG | | | | | --------------------------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 0 | BCON | Byte Control. BCON redefines HOLDb_OUT, BM0B_OUT, | | | | and BM1b_OUT as shown below. BCON is Read/Write. | | | | RESETb or STP=1 clears BCON. | ---------------------------------------------------------------------- ------------------------------------------------ | BCON | Pin 17 | Pin 16 | Pin 15 | ------------------------------------------------ | 0 | HOLDb_OUT | BM1b_OUT | BM0b_OUT | ------------------------------------------------ | 1 | BURSRQb_OUT | BUSAK0b_OUT| BYTE | ------------------------------------------------ ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 1 | ACON | ALE State Control. This bit defines the assertive | | | | state of ALEb_OUT when the NCR92C990 is in bus mater | | | | mode. ACON is Read/Write. RESETb or STP=1 clears | | | | ACON. | ---------------------------------------------------------------------- ----------------------------- | ACON | ALEb_OUT | ----------------------------- | 0 | Asserted High | ----------------------------- | 1 | Asserted Low | ----------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 2 | SWAP | Byte Swap. This bit allows the NCR92C990 to operate | | | | in systems that require bit 15:8 to be pointed to an | | | | even address and bits 7:0 to be pointed to an odd | | | | address. SWAP=1 allows the NCR92C990 to swap the | | | | HI/LO bytes on DMA transfers. Ring entries, INIT | | | | Block data is not swapped. SWAP is Read/Write and | | | | cleared by RESETb or STP=1. | ---------------------------------------------------------------------- | 8-3 | res | Reserved. Read as 0. | ---------------------------------------------------------------------- | 11-9 | TX-TX| Programmable TX IPG. Transmit IPG range with Control| | | IPG | /Status Register 3 (bit 15) = 1. | ---------------------------------------------------------------------- | 14-12| RX-TX| Programmable RX IPG. | | | IPG | | ---------------------------------------------------------------------- | 15 | IPGS | IPG Range Select with CSR3(15)=0 the default settings| | | | for TX-TX IPG and RX-TX IPG are selected. This is | | | | the normal power-up mode for the macrocell. If | | | | CSR(15)=1 then the contents of CSR3(14-7) select the | | | | programmable IPG values according to the tables | | | | shown. CSR3(15-3) are Write/Read but CSR(15-3) are | | | | read as 0. | ---------------------------------------------------------------------- TX IPG Range With CSR3(15)=1 -------------------------------------------- | Bit 11 | Bit 10 | Bit 0 | TX IPG Range | -------------------------------------------- | 0 | 0 | 0 | 9.6-10.4us | -------------------------------------------- | 0 | 0 | 1 | 11.2-12.0us | -------------------------------------------- | 0 | 1 | 0 | 12.8-13.6us | -------------------------------------------- | 0 | 1 | 1 | 14.4-15.2us | -------------------------------------------- | 1 | 0 | 0 | 16.0-16.8us | -------------------------------------------- | 1 | 0 | 1 | 17.6-18.4us | -------------------------------------------- | 1 | 1 | 0 | 19.2-20.0us | -------------------------------------------- | 1 | 1 | 1 | 20.8-21.6us | -------------------------------------------- With CSR3(15)=0, the TX-TX IPG Range = 9.5-10.2us TX-TX is defined as any transmission initiated by this node that follows either another transmission from this node, or any number of receive packets not addressed to this node, which followed a transmission from this node. The previous transmission need not have been successful. Example: TX - collided and backed off or was successful RX - no address match RX - no address match TX TX - follows NCR92C990 behavior: For TX-TX, the NCR92C990 begins the IPG count as soon as RENA_IN falls after the previous transmission or receive packet that was not received. Once the IPG count begins, it will ignore any reassertions of RENA_IN. After the IPG expires, if there is at least one byte of TX data in the FIFO, the NCR92C990 will begin to transmit. If the FIFO is empty, the NCR92C990 will continue to defer until the FIFO has at least one byte and then immediately begins to transmit. If between the time the IPG expires and the FIFO obtains one byte RENA_IN is asserted, the NCR92C990 will reset the IPG counter and wait until RENA_IN again falls. Once RENA_IN falls the IPG counter will again begin to count and the cycle is repeated. RX IPG Range -------------------------------------------------- | Receive followed by transmit IPG range. | | With Control/Status register 3(15)=1 | -------------------------------------------------- | Bit 14 | Bit 13 | Bit 12 | RX IPG Range | -------------------------------------------------- | 0 | 0 | 0 | 9.6 - 10.4us | -------------------------------------------------- | 0 | 0 | 1 | 11.2 - 12.0us | -------------------------------------------------- | 0 | 1 | 0 | 12.8 - 13.6us | -------------------------------------------------- | 0 | 1 | 1 | 14.4 - 15.2us | -------------------------------------------------- | 1 | 0 | 0 | 16.0 - 16.8us | -------------------------------------------------- | 1 | 0 | 1 | 17.6 - 18.4us | -------------------------------------------------- | 1 | 1 | 0 | 19.2 - 20.0us | -------------------------------------------------- | 1 | 1 | 1 | 20.8 - 21.6us | -------------------------------------------------- With CSR3(15)=0, the RX-TX IPG Range = 19.2 - 20.0us RX-RX is defined as any transmission initiated by this node when the last transaction processed by this node was any reception with a matching address whether it was a runt, missed packet, or a successful reception. Example: RX - addressed to this node (missed, runt or received) RX - not address match TX TX - follows NCR92C990 behavior: For RX-TX the IPG count begins as soon as RENA_IN falls for the previous receive (whether it was addressed to this node or not). If RENA_IN becomes reasserted during the first 3.2us of the IPG (minus synchronization delay), the IPG counter will be reset and wait until RENA_IN falls again to resume counting. Once the IPG count expires and the FIFO contains at least one byte, transmission will begin. If RENA_IN becomes reasserted after the first 3.2us of the IPG, the IPG counter will not be reset. Once the IPG counter expires and the FIFO contains at least one byte of TX data, transmission will begin. The FIFO cannot obtain 1 byte of data until RENA_IN falls or the packet is not addressed to this node and the NCR92C990 polls and begins to burst data. If between the time that the IPG expires and the FIFO contains at least 1 byte of data, RENA_IN is asserted, the IPG counter is reset, and waits until RENA_IN falls again. Once RENA_IN falls the IPG counter will again begin to count and the cycle is repeated. Buffer Management Receive Descriptor 0 15 0 -------------------------------------------------- | LAD | -------------------------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 15-0 | LAD | Low-order Address. These are the lowest 16 address | | | | bits of the buffer to which this descriptor points. | | | | They are written by the host. | ---------------------------------------------------------------------- Receive Descriptor 1 15 14 13 12 11 10 9 8 7 0 -------------------------------------------------------------- | OWN | ERR | FRA | OFL | CRC | BUF | SOP | EOP | HAD | -------------------------------------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 7-0 | HAD | High-order Address bits. These are the upper 8 | | | | address bits of the buffer to which this descriptor | | | | points. They are written by the host. The NCR92C990| | | | does not change these bits. | ---------------------------------------------------------------------- | 8 | EOP | End of Packet. This is the last buffer used by the | | | | NCR92C990 for this packet. If SOP=1 and EOP=1, the | | | | packet fits into one simple buffer. | ---------------------------------------------------------------------- | 9 | SOP | Start of Packet. This is the first buffer used by | | | | the NCR92C990 for this packet. If EOP and SOP are | | | | both set, the packet fits into one buffer. | ---------------------------------------------------------------------- | 10 | BUF | Buffer Error. This bit is set when the NCR92C990 | | | | does not own the next buffer while receiving a packet| | | | If a buffer error occurs, an OFL error may also occur| | | | but it is not reported unless both BUF and OFL occur | | | | at the same time. | ---------------------------------------------------------------------- | 11 | CRC | Cyclic Redundancy Check. This occurs when the | | | | receiver detects a CRC error on the incoming packet. | | | | CRC is valid only when EOP is set and OFL is not set.| ---------------------------------------------------------------------- | 12 | OFL | Receiver Overflow. This error indicates that the | | | | receiver has lost all or part of the incoming packet | | | | data because the temporary buffer overflowed. OFL is| | | | valid only when EOP is not set. | ---------------------------------------------------------------------- | 13 | FRA | Frame Error. This bit shows that the incoming packet| | | | contained a noninteger multiple of eight bits. FRA | | | | is not valid in internal loopback mode. FRA is valid| | | | only when EOP is set and OFL is not set. FRA should | | | | be ignored if no CRC error is reported. | ---------------------------------------------------------------------- | 14 | ERR | Error. This bit is set when at least one of the | | | | following bits is set: FRA, OFL, CRC, or BUF. | ---------------------------------------------------------------------- | 15 | OWN | This bit shows ownership of the descriptor entry. | | | | If OWN=0, the host owns this entry. If OWN=1, the | | | | NCR92C990 owns this entry. The host sets this bit | | | | after emptying the buffer to which this descriptor | | | | points. The NCR92C990 clears this bit after filling | | | | the buffer. If the host for the NCR92C990 has set | | | | this bit, for example, a buffer has been given over, | | | | the descriptor entries must not be changed. | ---------------------------------------------------------------------- Receive Descriptor 2 15 14 13 12 11 0 ------------------------------------- | 1 | 1 | 1 | 1 | BBL | ------------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 11-0 | BBL | Buffer Byte Length. This represents the length of | | | | the buffer to which this descriptor points. This | | | | number is expressed as a two's complement. BBL is | | | | written by the host. The NCR92C990 does not change | | | | BBL in any way. | ---------------------------------------------------------------------- | 15-12| 1 | These bits must be ones. This field is written by | | | | the host. The NCR92C990 does not change these bits. | ---------------------------------------------------------------------- Receive Descriptor 3 15 12 11 0 ------------------------------------------------ | res | MBL | ------------------------------------------------ ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 11-0 | MBL | Message Byte Length. This represents the length of | | | | the received message in bytes. MBL is valid only | | | | when ERR is clear and EOP is set. MBL is written by | | | | the NCR92C990 and cleared by the host. | ---------------------------------------------------------------------- | 15-12| res | Reserved. These bits are reserved and read as zeros.| ---------------------------------------------------------------------- Transmit Descriptor 0 15 0 ---------------------------------------- | LAD | ---------------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 15-0 | LAD | Low-order Address. These are the lowest 16 address | | | | bits of the buffer to which this descriptor points. | | | | They are written by the host. The NCR92C990 does | | | | not change these bits. | ---------------------------------------------------------------------- Transmit Descriptor 1 15 14 13 12 11 10 9 8 7 0 ------------------------------------------------------------- | OWN | ERR | res | MOR | ONE | DEF | SOP | EOP | HAD | ------------------------------------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 7-0 | HAD | High-order Address bits. These are the 8 address | | | | bits of the buffer to which this descriptor points. | | | | They are written by the host. The NCR92C990 does not| | | | change these bits. | ---------------------------------------------------------------------- | 8 | EOP | End of Packet. This is the lastbuffer used by the | | | | NCR92C990 for this packet. If EOP and SOP are both | | | | set, the packet fits into a single buffer. EOP is | | | | set by the host. The NCR92C990 does not alter EOP. | ---------------------------------------------------------------------- | 9 | SOP | Start of Packet. This is the first buffer used by | | | | the NCR92C990 for this packet. If EOP and SOP are | | | | both set, the packet fits into one buffer. SOP must | | | | = 1 in the first buffer of a packet or it will be | | | | skipped over during a pull until the OWN bit and | | | | SOP bits are set. | ---------------------------------------------------------------------- | 10 | DEF | Deferred. This means that the NCR92C990 had to defer| | | | while trying to transmit a packet. This occurs if | | | | the channel is busy when the NCR92C990 is ready to | | | | transmit. | ---------------------------------------------------------------------- | 11 | ONE | One. This means that exactly one retry was necessary| | | | to transmit a packet. ONE is not valid if LCOL is | | | | set. | ---------------------------------------------------------------------- | 12 | MOR | More. This means that more than one retry was | | | | necessary to transmit a packet. | ---------------------------------------------------------------------- | 13 | res | Reserved. The NCR92C990 writes a zero to this bit. | ---------------------------------------------------------------------- | 14 | ERR | Error. This bit is set when at least one of the | | | | following bits is set: RTY, CLOS, LCOL, or UFL. | ---------------------------------------------------------------------- | 15 | OWN | This bit shows ownership of the descriptor entry. | | | | If OWN=0, the host owns this entry. If OWN=1, the | | | | NCR92C990 owns this entry. The host sets this bit | | | | after emptying the buffer to which this descriptor | | | | points. The NCR92C990 clears this bit after filling | | | | the buffer. Once either the host or NCR92C990 has | | | | given over a buffer, it must not alter the descriptor| | | | entry. | ---------------------------------------------------------------------- Transmit Descriptor 2 15 14 13 12 11 0 --------------------------------------------- | 1 | 1 | 1 | 1 | BBL | --------------------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 11-0 | BBL | Buffer Byte Length. This represents the length of | | | | the buffer to which this descriptor points. This | | | | number is expressed as a two's complement. BBL is | | | | written by the host. The NCR92C990 does not change | | | | BBL in any way. | ---------------------------------------------------------------------- | 15-12| 1 | Thes bits must be ones. This field is written by the| | | | host. The NCR92C990 does not change these bits. | ---------------------------------------------------------------------- Transmit Descriptor 3 15 14 13 12 11 10 9 0 ----------------------------------------------- | BUF | UFL | res | LCOL | CLOS | RTY | TDR | ----------------------------------------------- ---------------------------------------------------------------------- | Bits | Name | Description | ---------------------------------------------------------------------- | 9-0 | TDR | Time Domain Reflectometry. This bits shows the state| | | | of a counter internal to the NCR92C990. This counter| | | | counts from the start of a transmission to a | | | | collision if one occurs. This value can be used to | | | | determine the approximate distance to a fault in a | | | | cable. TDR is valid and written by the NCR92C990 | | | | only if RTY is set. | ---------------------------------------------------------------------- | 10 | RTY | Retry. This error indicates that the transmitter | | | | has failed because of collisions in 16 attempts to | | | | successfully transmit a packet. If the Disable | | | | Retry (DRY) bit in the mode register is set, RTY will| | | | set after only one failed transmission attempt. | ---------------------------------------------------------------------- | 11 | CLOS | Carrier Loss. This bit is set when the carrier | | | | input to the NCR92C990 goes low during a transmission| | | | The NCR92C990 does not try again when it loses the | | | | carrier; it transmits the entire packet until | | | | complete. CLOS is not valid during internal loopback| ---------------------------------------------------------------------- | 12 | LCOL | Late Collision. This bit means that a collision | | | | occurred after the channel slot-time (64 bytes) | | | | elapsed. The NCR92C990 does not retry on late | | | | collisions. | ---------------------------------------------------------------------- | 13 | res | Reserved. The NCR92C990 sets this bit to 0. | ---------------------------------------------------------------------- | 14 | UFL | Underflow. This error indicates that the transmitter| | | | has shortened a message because the data was late | | | | coming from memory. UFL indicates that the temporary| | | | buffer emptied before the end of the packet. The | | | | transmitter is turned off and TON set = 0. | ---------------------------------------------------------------------- | 15 | BUF | Buffer Error. This bit is set during transmission | | | | when the NCR92C990 cannot find the EOP=1 in the | | | | current buffer and does not own the next buffer. | | | | BUF is set by the NCR92C990 and cleared by the host. | | | | If a buffer error occurs, an underflow error also | | | | occurs. The transmitter is turned off and TON set | | | | = 0. | ---------------------------------------------------------------------- NCR92C990 Changes and DIfferences to the Am7990 In engineering the NCR92C990, NCR noticed discrepancies in the way the Am7990 operated and the way the documentation read. A summary follows of these items that are most significant to hardware and software designers. Documented 1. The Am7990 documentation states that the initialization block must begin on an even word address. Odd-byte initialization addresses cause the Am7990 to operate in an undefined manner. The NCR92C990 accepts odd-byte initialization block addressing in addition to the standard even-byte addressing. In odd-byte addressing, the address increments by one after the first DMA transfer from the odd-byte address to get on an even boundary. Then the address counter increments by two, as with even-byte addressing. 2. The Am7990 documentation states that no DMA bursts occur between polling and loading of DMA cycles. Under certain circumstances, the Am7990 actually performs DMA bursts between the polling and loading DMA cycles (ring access). Undocumented 1. The Am7990 asserts the INTRb output 25.5 cycles after the rise of HOLDb on the last initialization DMA read cycle. The NCR92C990 asserts INTRb after completing 1.5 cycles after the rise of the HOLDb output on the last initialization DMA read cycle. 2. Because of timing differences in the response time to a receive-based collision and the transfer of received data to the FIFO, responses may differ on the NCR92C990 if the collision signal is asserted during the header, between the destination and the source addresses of a receive packet, or during the 64th data byte. In the dirst case, the lack of a sync bit causes the abort. In the second case, an address mismatch causes the abort. In the third case, a runt packet causes a CRC and framing error. It is possible for one of these aborts or errors in the Am7990 to appear as one of the others in the NCR92C990. 3. When the first DMA transfer is a data word, the Am7990 starts transmitting eight cycles after the rising edge of the DASb pulse. If the first DMA transfer is only a byte, the Am7990 starts the transmission 12 cycles after the rising edge of the DASb pulse. In both the byte and word cases, the NCR92C990 starts transmission eight cycles after the rising edge of DASb. 4. During loopback, the rising edge of the DASb pulse latches in the last byte/word of a transmission. The Am7990 begins transmission of the next packet preamble on the rising edge of DASb. The NCR92C990 begins transmission within five clock cycles after the rising edge of DASb. 5. During external loopback, the Am7990 SILO can lose some data if there is heavy traffic on the media. The NCR92C990 does not lose data, even during heavy traffic on the media. 6. The Am7990 generates a memory error if READYb has not been asserted within 254 cycles after DASb falls and both the transmitter and receiver are turned off. If READYb falls between 251 and 253 cycles after DASb falls, incorrect data is loaded into Control/Status Register 0, the memory error (ME) bit is set, but neither the transmitter nor receiver are turned off. The NCR92C990 matches this behavior. 7. The Am7990 requires 11 clock cycles after the rising edge of HOLDb to set the missed packet (MP) bit in the Control/Status Register 0. The NCR92C990 sets the MP bit within two clock cycles of the rising edge of HOLDb. 8. If the SILO overflows during a receive operation, the Am7990 updates the ring with thenumber of bytes actually transferred to memory at that point. The NCR92C990 updates the ring with the number of bytes transferred to the memory, plus any that may be left in the FIFO when the overflow occurred. The data in the FIFO is not actually transferred to memory. Because the packet is incomplete, the host should ignore all the data in the buffer, and the actual amount of data in the buffer should not be considered. 9. The Am7990 begins Time Domain Reflectometry (TDR) counts from the assertion of RENA. The NCR92C990 begins TDR counts 2-3 cycles after the assertion of TENA, as specified in the IEEE 802.3 specification. TDR counts are only valid after a retry. During TX updates when a retry does not occur, the Am7990 writed invalid TDR values to the ring. The NCR92C990 also writes invalid TDR data to the ring, but not necessarily the same values. 10.The Am7990 recognizes a defer condition when it is ready to assert TENA at the start of transmission, but RENA is already asserted. The NCR92C990 recognizes a defer condition when it is ready to assert TENA at the start of a transmission and either RENA is already asserted or the interpacket gap time has not elapsed since RENA went inactive. 11.If the SILO on the Am7990 contains 43 or more bytes of data from a previous reception and another packet is being sent by another node on the network, an overflow condition can occur even if the second packet is not addressed to this node. For example: 43 bytes of data remain in the SILO from a previous packet reception. The Am7990 checks the incoming packet for a valid destination address and, in the process, tries to transfer the six address bytes to the SILO. It recognizes that the address is not its own after the sixth byte, but before that happens, an overflow of the 48-byte SILO occurs (43 + 6 = 49). The Silo pointer is reset to the 44th byte in the FIFO, but the packet residing in the SILO is labeled with an overflow error. The NCR92C990 temporarily stores the incoming destination address in a seperate FIFO which is either erased if the address is not matches, or burst into the main 48-byte FIFO if the address is matched. No overflow is reported by the NCR92C990 in the previous example. 12.Defer is reported if the first attempt to transmit a packet is delayed because RENA is asserted when the NCR92C990 is ready to transmit (the IPG has expired and the TX FIFO contains at least one byte of data); or, for an RX-TX transmission, defer is reported if the NCR92C990 is ready to transmit and the IPG time has not expired. 13.Interpacket gap: Either TX-TX or RX-TX. In general, three conditions are required in order to begin a transmission: - The backoff count is 0 (only pertains to retries) - The IPG has expired. - The TX FIFO contains at least 1 byte of data. The AM7990 TX FIFO is reset (and thus empty) whenever RENA is asserted except when: - TENA is also asserted, or - RENA is still asserted from a previous transmission, or - An RX packet is still on the network but the RX circuitry has determined that it is not addressed to this node. Therefore, the NCR92C990 will defer to any incoming packet, regardless of the state of the IPG counters except for a packet which causes RENA to be asserted just before TENA is to be asserted for transmission. The NCR92C990 IPG counter will be reset if the RENA pulse is shorter than the remainder of the IPG as programmed. The IPG features control IPG timings which are different for RX-TX, TX-TX and the default IPG partition. If the NCR92C990 is ready to transmit and is waiting for the IPG to expire, it will defer to the incoming packet thus avoiding a collision. TX-TX The Am7990 data sheet refers to the condition that if RENA is asserted within the first 4.1us of the IPG after a TX that the Am7990 will defer to the packet and receive it if the sync bit is correctly recognized after the first 4.1us of the IPG. The NCR92C90 will begin to look for the sync immediately. RX-TX The Am7990 data sheet refers to the condition that if RENA is asserted within the first 4.1us of the IPG after a RX that the Am7990 will defer to the packet and not receive it. The NCR92C990 will defer to the packet and will receive it.