NCR89C100 Chip Specification Overview The NCR89C100 is designed for low-cost, SBus-based systems. It incorporates standard workstation I/O devices with a DMA controller in a single 160-pin PQFP package, providing cost, area, and power savings over discrete implementations. The 89C100 provides three special purpose SBus DMA channels that are commonly used on SPARC platforms; Ethernet, SCSI, and Parallel Port. It consists of three major logic blocks: DMA2, ENET, SCSI as well as an additional TEST block. The DMA2 block provides internal buffering for each of its three channels in the form of a cache for the ENET interface and fifos for SCSI and Parallel Port interfaces. It also provides control-status registers for each channel, plus several SCSI/PPORT-specific support registers, and a write buffer for slave accesses to the ENET. The DMA2 block design is based on the L64853 ASIC design with the addition of a programmable, Centronics-type parallel port. It incorporates a number of new features for increasing performance and allowing different modes of operation necessary for future desktop systems. The ENET block is based on the NCR92C990 Application Specific Function (ASF) which is a superset of (and fully backwards compatible with) the AM7990 previously found on SPARCstations. The SCSI block is based on the NCR53C9X ASF which is a superset of (and fully backwards compatible with) the NCR53C90A also found on SPARCstations. The TEST block contains the JTAG TAP controller, JTAG boundary scan cells, ASF test muxes and some ancillary glue logic. The 89C100 interfaces directly to the SBus with no additional glue logic. Together, with the 89C105 (slave I/O), it provides the core SPARCstation I/O subsystem. This document reflects the integrated nature of the 89C100. This section, "NCR89C100 Master I/O", covers the chip as a whole and describes pinout information, test muxing, chip-level block diagrams and address map, and electrical and mechanical characteristics. The TEST block is described in detail, but DMA2, ENET, and SCSI blocks are only introduced and a list of differences from their discrete implementations is given. The full specifications for those discrete implementations follow in the next three sections: "DMA2 DMA Core", "NCR92C990 Ethernet Core," and "NCR53C9X SCSI Core". These specifications cover functional descriptions and theory of operations. Features Single chip solution to standard SPARC DVMA devices - saves cost, power, board space, and weight. Together, with the 89C105 chip, forms a two-chip solution which provides the core SPARCstation I/O subsystem. Supports concurrent 10 MByte/sec SCSI transfers, 1.25 MByte/sec Ethernet transfers, and 4 MByte/sec Parallel Port transfers. Supports 4-word, 8-word, and 'no burst' Sbus burst modes. 64-byte internal cache for Ethernet data buffering. 64-byte internal FIFOs for SCSI and Parallel Port data buffering 16-bit write buffer for slave writes to Ethernet Improved address and byte count registers with "NEXT" address/byte count features for data block chaining on SCSI and Parallel Port interfaces. JTAG internal and boundary scan for improved chip and board level testability. Intended Applications The 89C100 is intended for low-end SBus-based systems in which cost, power, and area are the main design constraints. It is designed for use with either the Texas Instruments MicroSPARC or SuperSPARC processors, but will also work in any SBus-based system. Related Products The 89C100 is designed to share a single SBus slot with the NCR89C105. Functional Description Overview The 89C100 integrates the SBus DMA2 Controller, the NCR92C990 802.3 LAN Controller, and the NCR53C9X Fast SCSI Processor in a 160-pin plastic quad flat package (PQFP). The programmer's interface is identical to that of a discrete implementation using the above ICs. The chip-level address map is defined in the next section. Refer to "DMA2 DMA Core", "NCR92C990 Ethernet Core," and "NCR53C9X SCSI Core" for mor einformation on the above devices. 89C100 and 89C105 Interdependencies When the 89C100 and the 89C105 are used together, the 89C105 receives three clocks from the 89C100 (fpy_clk24, fpy_clk32, and scc_clk_20). The 89C100 simply provides oscillator pads on its pins because of a pin limitation on the 89C105. The 89C100 doe snot use these clock signals internally. The 89C100 also sends its three interrupt signals to the 89C105 for processing, they are; sb_d_irq_, sb_e_irq_, and sb_p_irq_ for; SCSI, Ethernet, and parallel port interrupts, respectively. Refer to "NCR89C105 Slave I/O" for a description of how the 89C105 handles interrupts. It is necessary to provide both enet_tclk and scsi_clk even if the Ethernet controller and SCSI controller are not used. Technology The 89C100 is a standard cell design, based on the NCR VS700H technology (.95 u drawn, .7 effective). It consists of 60,000 equivalent gates. Start-Up Information The 89C100 receives a reset from the SBus signal sb_reset_. This signal must be asserted for at least 512 SBus clock cycles after the system power is stable, as specified by SBus specification B.0. After this, the 89C100 is ready for programming. Functional Blocks Overview This section includes block diagrams, descriptions, and block-level address maps for the following: - DMA2 Block - SCSI Block - Ethernet Block - Test Block DMA2 Block The DMA2 block is functionally and logically equivalent implementation of the L63854 SBus DMA controller with two minor differences. Differences - E_CSR bit 20, E_ALE/AS_ is not implemented. This allows use of other ENET controllers which is only an option in a discrete implementation. - The pullup for the id_cs_ pin is provided internally. To use an external PROM simply connect id_cs_ with the PROM chip select pin. To signify absense of an external PROM connect id_cs_ to logic low. DMA2 Level Address Map sb_pa(w x y) sb_pa(27:0) Register Accessed Type Size ------------------------------------------------------------------------------ | 0 0 0 | 0x800 0000 | Internal ID Register | R | 32 | ------------------------------------------------------------------------------ | | 0x840 0000->| DMA2 ESP Registers | | | | | 0x840 000f | | | | | | | | | | | 0 0 1 | 0x840 0000 | Control/Status Register (D_CSR) | R/W | 32 | | 0 0 1 | 0x840 0004 | Address Register (D_ADDR) | R/W | 32 | | 0 0 1 | 0x840 0008 | Byte Count Register (D_BCNT) | R/W | 24 | | 0 0 1 | 0x840 000c | Test Control/Status Reg(D_TST_CSR)| R/W | 32 | | | | | | | ------------------------------------------------------------------------------ | | 0x840 0010->| DMA2 Ethernet Registers | | | | | 0x840 001f | | | | | | | | | | | 0 0 1 | 0x840 0010 | Control/Status Register (E_CSR) | R/W | 32 | | 0 0 1 | 0x840 0014 | Test Control/Status Reg(E_TST_CSR)| R/W | 32 | | 0 0 1 | 0x840 0018 | Cache Valid Bits (E_VLD) | R/W | 32 | | 0 0 1 | 0x840 001c | Base Address Reg (E_BASE_ADDR) | R/W | 8 | | | | | | | ------------------------------------------------------------------------------ | | 0xc80 0000->| DMA2 Parallel Port Registers | | | | | 0xc80 001f | | | | | | | | | | | 1 1 0 | 0xc80 0000 | Control/Status Register (P_CSR) | R/W | 32 | | 1 1 0 | 0xc80 0004 | Address Register (P_ADDR) | R/W | 32 | | 1 1 0 | 0xc80 0008 | Byte Count Register (P_BCNT) | R/W | 32 | | 1 1 0 | 0xc80 000c | Test Control/Status Reg(P_TST_CSR)| R/W | 32 | | 1 1 0 | 0xc80 0010 | Hardware Config Register (P_HCR) | R/W | 16 | | 1 1 0 | 0xc80 0012 | Operation Config Register (P_OCR) | R/W | 16 | | 1 1 0 | 0xc80 0014 | Parallel Data Register (P_DR) | R/W | 8 | | 1 1 0 | 0xc80 0015 | Transfer Control Register (P_TCR) | R/W | 8 | | 1 1 0 | 0xc80 0016 | Output Register (P_OR) | R/W | 8 | | 1 1 0 | 0xc80 0017 | Input Register (P_IR) | R/W | 8 | | 1 1 0 | 0xc80 0018 | Interrupt Control Register (P_ICR)| R/W | 16 | ------------------------------------------------------------------------------ SCSI Block The SCSI block is based on the NCR53C9X ASF which is a superset of (and fully backward compatible with) the NCR53C90A previously found on SPARCstations. Differences The 89C100 implementation of the SCSI channel differs from former discrete implementations as follows: - The following pins exist in the discrete implementation but not in the 89C100 chip: - TGS, IGS, DIFFM--Not needed for single-ended SCSI - RESETO--Not normalls used in a system - All current SPARCstation designs operate as single-ended SCSI only, with the RESETO pin floating so this was chosen for the 89C100. - The NCR53C9X ASF has two additional registers: - Configuration Register 3 (used to enable Fast SCSI) - Transfer Count High (allows for up to 16MB block transfers) - The NCR53C9X ASF can be clocked at 40 Mhz (necessary for Fast SCSI). Software using hardware clocked at this speed will need to adjust the Clock Conversion Factor Register accordingly. SCSI-Level Address Map sb_pa(w x y) sb_pa(27:0) Register Accessed Type Size ------------------------------------------------------------------------------ | | 0x880 0000->| SCSI Controller Registers | | | | | 0x880 003f | | | | | | | | | | | 0 1 0 | 0x880 0000 | Transfer Count Low (7:0) | R/W | 8 | | 0 1 0 | 0x880 0004 | Transfer Count Middle (15:8) | R/W | 8 | | 0 1 0 | 0x880 0008 | FIFO Data | R/W | 8 | | 0 1 0 | 0x880 000c | Command | R/W | 8 | | 0 1 0 | 0x880 0010 | Status | R | 8 | | 0 1 0 | 0x880 0010 | Select-Reselect Bus ID | W | 8 | | 0 1 0 | 0x880 0014 | Interrupt | R | 8 | | 0 1 0 | 0x880 0014 | Select-Reselect Time-Out | W | 8 | | 0 1 0 | 0x880 0018 | Sequence Step | R | 8 | | 0 1 0 | 0x880 0018 | Synchronous Transfer Period | W | 8 | | 0 1 0 | 0x880 001c | FIFO Flags | R | 8 | | 0 1 0 | 0x880 001c | Synchronous Offset | W | 8 | | 0 1 0 | 0x880 0020 | Configuration #1 | R/W | 8 | | 0 1 0 | 0x880 0024 | Clock Conversion Factor | W | 8 | | 0 1 0 | 0x880 0028 | Test (Chip Test Use Only) | W | 8 | | 0 1 0 | 0x880 002c | Configuration #2 | R/W | 8 | | 0 1 0 | 0x880 0030 | Configuration #3 | R/W | 8 | | 0 1 0 | 0x880 0038 | Transfer Count High (23:16) | R/W | 8 | ------------------------------------------------------------------------------ Ethernet Block The ENET block is based on the NCR92C990 ASF which is a superset of (and fully backwards compatible with) the AM7990 previously found on SPARCstations. Differences The only differences between the NCR92C990 and the AM7990 are: - Programmable Inter Packet Gap (IPG). The NCR92C990 allows one to program the Transmit after Transmit (Tx-Tx) or Transmit after Receive (Rx-Tx) IPG time within the range of 9.6 u sec (the Ethernet spec minimum IPG) to 22.4 u sec. This feature can be accessed via the upper bits of CSR3, as shown below: CSR3 bit Description 15 Enable programmable IPG (default is 0, not programmable) 14-12 Rx-Tx IPG value: (default=110 or 20.8 u sec) 11-9 Tx-Tx IPG (default=000 or 9.6 u sec) 8-0 As normally defined in AM7990 NOTE: - The formula for calculating the IPG value is [9.6 + 1.6 * (3 bit IPG #)] u sec - The default values chosen to closely mimic the operation of the AM7990. The programmable IPG time assumes its default value should ANY of the following occur: - Ethernet hard reset (either as a result of an SBus reset or the E_CSR E_RESET bit of the DMA2). - The CSR0 STOP bit is set. - The CSR0 INIT bit is set. - The CSR3 Enable programmable IPG is reset to 0. Software drivers should set CSR3 right after the last INIT, while waiting for the IDON interrupt. It is recommended that the Enable, Rx-Tx IPG and Tx-Tx IPG fields be ORed into all CSR3 writes. - The NCR92C990 core used in the 89C100 differs from both the AS7990 and the stand-along NCR92C990 core with respect to the memory error (MERR) time-out value. The description for bit 11 (ME) in the Control/Status Register 0 tables shows that READYb_IN must be received within 25.6us (4X) to avoid memory errors in high latency systems. This feature helps to avoid unneeded reinitializations of the NCR92C990 during periods of high system activity. Refer to "NCR92C990 Ethernet Core" for details. Ethernet-Level Address Map sb_pa(w x y) sb_pa(27:0) Register Accessed Type Size ------------------------------------------------------------------------------ | | 0x8c0 0000->| Ethernet Controller Registers | | | | | 0x8c0 0003 | | | | | | | | | | | 0 1 1 | 0x8c0 0000 | Register Data Port (RDP) | R/W | 16 | | 0 1 1 | 0x8c0 0002 | Register Address Port (RAP) | R/W | 16 | ------------------------------------------------------------------------------ Test Block The 89C100 contains an IEEE JTAG 1149.1 compliant test controller and boundary scan architecture. All mandatory instructions are supported, and this document contains the chip specific boundry scan information. The 89C100 also contains internal test logic and reserved instructions. The basic description of the logic appears below but is not supported. This section describes the goals and implementation of the testability features implemented in the 89C100. These features have been incorporated to provide a structures test approach to both device fabrication testing and board-level testing and debug. JTAG Scan Access The goals for the 89C100 testability are to provide for high stuck at fault coverage at both the IC and board level. This isprovided by the incorporation of an IEEE 1149.1 (JTAG) compatible TAP controller and boundary scan, which in conjunction with the modular broadside access modes provides access to each of the major functional blocks on the I/O chips through either full scan (in the case of the DMA2 block) or boundary scan (in the case of the NCR ASFs). These ASFs are tested during device fabrication by a full broadside pin mode that provides direct access to all ports of each ASF from the device pins. This allows standardized test patterns to be applied directly to each ASF without the need for additional high fault coverage patterns for these blocks. At the board-level, the JTAG compatible boundary scan provides for complete access to PCB interconnect, including die to package bonding. Block Access Modes Diagnostic multiplexing between the pad ring and the internal ASFs is configurable into four different modes: Normal Mode, in which the device operates as required in the system; TBLK1 Mode, for scanned logic, in which all the ports to the DMA2 logic are accessible via scannable elements. In addition, the internal scan chain of the block is connected in series with the boundary scan chain, and the partition scan chain (if one is required) to form a complete scan path for access to all state and primary inputs of the block. TBLK2 and TBLK3, for NCR designed logic, in which each block is presented to the pins of the device as if it were a stand-alone device. Tristate Pin Function All output pins of the device are tristate-able, controlled by elements in the boundary scan chain, to support manufacturing system test. At pwoer-up and in normal operation of the system this function is disabled by the TRSTB JTAG pin being held in the active low state. Block Diagnostic Modes TBLK1 (internal Scan) Diagnostic Mode Figure 2-1 illustrates the operation of the TBLK1 diagnostic mode. In this mode, the test logic is configured to connect every primary input to the Q-output of a scannable flip-flop and every primary output to the D-input of a scannable flip-flop. In addition, every flip-flop inside the block is configured into a single scan chain, known as the internal, or "iscan" chain. TBLK2/TBLK3 Diagnostic Mode Figure 2-2 illustrated the operation of the TBLK2(TBLK3) diagnostic mode. In these modes the test logic is configured to connect internal inputs and outputs to BLK2 (BLK3) to pins normally assigned to BLK1 or BLK3 (BLK2). SInce these blocks are non-scannable, the only function of the JTAG controller in this mode is to configure the multiplexor logic into this mode. Hence the scan datapath is placed in BYPASS mode. Output of the block that are normally connect to BLK1 are multiplexed into the chip outputs of the other blocks, configured by the TBLK2 (TBLK3) mode signal. Inputs to BLK2 (BLK3) are multiplexed with inputs from the other blocks. Figure 2-2 shows how the outputs of BLK2 and the inputs of BLK3 are configured. Other JTAG test modes (TBLK2_BS and TBLK3_BS) are provided that operate identically except that the scan data path is configured to pass through the boundary chain. This allows application of the broadside test vectors to the blocks using the boundary cahin to drive primary inputs and sample primary outputs in a pseudo-static manner, i.e. it does not directly support complex edge relationships between inputs. Instead these vectors must be "exploded" into multiple boundary scan vectors. JTAG Controller The JTAG controller contains the follow elements: - NCR Tap controller - Scan Datapath including instruction register, bypass register and ID register - Clock control register and state machine The follow figure shows a simplified block diagram of the JTAG controller. It has been partitioned into two main functional areas: Scan Datapath and Scan Control Logic. The NCR tap controller is a standard cell implementation of a reference 1149.1 tap state machine. It is connected directly to the test access port on the 89C100 (TCK, TMS, TRSTB) and generates the basic scan controls (clock_dr, clock_ir, reset_l, select, shift_dr, shift_ir, update_dr, update_ir) which are used to control the scan architecture. The NCR TAP implementation has been modified slightly to also make available the TAP state for use by supplemental state machines. The NCR state machine implements the reference state diagram described by the 1149.1 specification. The state coding is shown in Table 2-12. Table 2-11 State Assignments for NCR TAP controller ---------------------------------------------------------- | Controller State | State[3:0] | ---------------------------------------------------------- | Exit2-DR | 0 | ---------------------------------------------------------- | Exit1-DR | 1 | ---------------------------------------------------------- | Shift-DR | 2 | ---------------------------------------------------------- | Pause-DR | 3 | ---------------------------------------------------------- | Select-IR-Scan | 4 | ---------------------------------------------------------- | Update-DR | 5 | ---------------------------------------------------------- | Capture-DR | 6 | ---------------------------------------------------------- | Select-DR-Scan | 7 | ---------------------------------------------------------- | Exit2-IR | 8 | ---------------------------------------------------------- | Exit1-IR | 9 | ---------------------------------------------------------- | Shift-IR | A | ---------------------------------------------------------- | Pause-IR | B | ---------------------------------------------------------- | Run-Test/Idle | C | ---------------------------------------------------------- | Update-IR | D | ---------------------------------------------------------- | Capture-IR | E | ---------------------------------------------------------- | Test-Logic-Reset | F | ---------------------------------------------------------- The instruction register for the 89C100 is a 4-bit register comprised of simple scannable elements. When the TAP state machine issues a reset signal this register is initialized to the IDCODE(1110) instruction. The parallel inputs of the instruction register are not used to load design-specific information and are tied-off to logic 0. The 4-bit output of the instruction register is followed by an instruction decode stage which decodes up to 16 unique instructions. Not all of these are used by the89C100 but are given mnemonics for completeness. Table 2-12 Decoded JTAG Instructions ------------------------------------------------------------------ | Value | Mnemonic | Description | ------------------------------------------------------------------ | 0000 | EXTEST | Boundary scan board interconnect test. | ------------------------------------------------------------------ | 0001 | SAMPLE | Boundary scan sample/period. | ------------------------------------------------------------------ | 0010 | TBLK1 | BLK1 ATPG scan test mode (Internal+- | | | | Boundary+Clock chains). | ------------------------------------------------------------------ | 0011 | TBLK2 | BLK2 broadside test mode (Bypass). | ------------------------------------------------------------------ | 0100 | TBLK3 | BLK3 broadside test mode (Bypass). | ------------------------------------------------------------------ | 0101 | RESERVED | -- | ------------------------------------------------------------------ | 0110 | PSCAN | Reserved for partition scan (if | | | | implemented, otherwise Bypass). | ------------------------------------------------------------------ | 0111 | INTEST | Boundary scan capture of internal I/O. | ------------------------------------------------------------------ | 1000 | TBLK2_BS | BLK2 boundary scan test mode. | ------------------------------------------------------------------ | 1001 | TBLK3_BS | BLK3 boundary scan test mode. | ------------------------------------------------------------------ | 1011 | TPSCAN | Reserved for BLK1 tester partition scan | | | | mode (if implemented, otherwise Bypass).| | | | Other BLK1 pins controlled by broadside | | | | tester. | ------------------------------------------------------------------ | 1100 | BPSCAN | Reserved for BLK1 boundary partition | | | | scan mode (if implemented, otherwise | | | | Bypass). Other BLK1 pins controlled | | | | by boundary scan. | ------------------------------------------------------------------ | 1101 | ZMODE0 | General purpose test mode. | ------------------------------------------------------------------ | 1110 | IDCODE | Device ID register. | ------------------------------------------------------------------ | 1111 | BYPASS | Bypass mode. | ------------------------------------------------------------------ The scan controls decoded by these instructions configure the scan data path, the test multiplexors and control the clocks and pseudo clocks for the test mode in progress. Instruction Decode The I-Decode logic converts the 4-bit instruction register contents into decoded signals that control mux selection in the scan datapath and test mode configuration in the ASFs. Nine of these signals are latched by the I-latch to provide glitch free values on these signals which are updated during the IR-Update state. Clock Control FSM The clock control finite state machine monitors the state output from the NCR TAP controller and determines when it is necessary to insert the capture clock adn/or pseudo clocks required to support ATPG stimulus application to BLK1. The clock gating is designed such that the boundary clock is guaranteed to be asserted at all elements of the boundary scan chain before it is applied to either the clock or pseudo clock (set/reset) inputs to the BLK1 internals. This requirement is present due to the fact that ATPG vectors have an assumed order in which stimulus is applied to the circuit and state or primary outputs are captured. The clock control state machine in the 89C100 has been verified to support the requirements of TestScan ATPG from Cadence Design Systems, Inc. although it may function equally well with other ATPG systems. The assumed sequence of operations required for ATPG pattern applications is: 1) Stimulate pins - boundary and pscan chains shift/update sequence 2) Stimulate shift register/latches - internal scan chain shift in 3) Measure pins - boundary and pscan chain capture sequence. 4) Puls clocks/pseudo clocks - internal chain clock/set/reset. 5) Measure shift register/latches - internal scan chain shift out. The Clock Control FSM has been designed to support this event ordering in a single continuous shift-update-capture-shift sequence. In TBLK1 mode the scan chains within the 89C100 are concatenated into a single chain containing internal, boundary and clock control scan chains. Hence after an initial shift-update sequence, the requirements of (1) and (2) have been met. The Capture-DR state is then used to measure the state of the primary outputs of BLK1 by issuing a clock to the boundary with the shift control not asserted. A delayed version of the clock (or update pulse in the case of the pseudo clocks) is then used to apply clock, set or reset to the internal scan chain to implement the internal chain capture. This occurs only when indicated by the value of the "capture" output from the clock control state machine. Clock Control Register The other three bit positions in the clock control scan chain are transferred to the clock control register during a DR-update sequence, when theya re decoded by the C-Decode logic to specify which vector class the following capture sequence belongs to out of the following categories: 1) Shift only, no capture 2) Capture scan chain, (i.e. shift high during capture clock). 3) Normal clocked vector 4) Set vector, no clock. 5) Reset vector, no clock. Since the last two categories are only required when the logic under test contains asynchronous sets or resets, they are not required for the 89C100. Mode Gating Logic The decoded vector type information is combined with the clock control FSM information and the primary scan controls from the NCR TAP controller and instruction register decoded to generate control signals for each of the four scan chains with the 89C100: iscan, bscan, pscan (if present) or cscan. These signals are buffered and disctributed throughout the device to the various chain elements. Since the 89C100 does not require a partition scan cahin for its final implementation, these controls have been deleted. Scan Datapath The scan datapath within the JTAG COntroller contains the chain configuration logic, implemented as a series of multiplexors; inter-chain flops to guarantee hold margins; the Cscan register; JTAG compliant ID, BYPASS and IR shift registers and the TDO output multiplexors and flop. This datapath, like the external scan chains and test logic is controlled by the scan control logic described above. The only variation from a more conventional IEEE 1149.1 implementation is the ability to configure the scan chain into various different modes based on the instruction type. The use of the hold flops, clocked by TCK~ is simply an implementation detail to reduce the effects of clock skew between the separate scan chains. The 89C100's scan datapath does not include a partition scan chain, as in its final implementation this functionality has been incorporated into the internal, or "iscan" chain the facilitate physical implementation of the device. The elements of the embedded partition scan cahin are therefore controlled by the same datapath controls as the existing chain elements. Table 2-14 lists the lengths of the various chains that comprise the 89C100's scan datapath. Table 2-13 89C100 JTAG Chain Lengths ------------------------------------------------------------------ | Chain Name | Number of Elements | ------------------------------------------------------------------ | BYPASS | 1 | ------------------------------------------------------------------ | I.D. | 32 | ------------------------------------------------------------------ | Instruction Register | 4 | ------------------------------------------------------------------ | Internal | 893 | ------------------------------------------------------------------ | Boundary | 209 | ------------------------------------------------------------------ | ATPG | 1105 | ------------------------------------------------------------------ Performance The design as implemented in NCR's VS700H 0.94um (drawn) standard cell library has been verified to oerate at a 5MHz scan rate. The JTAG controller occupies approximately 700 gates, and the scan overhead for the simple multiplexed flop scan element that it supports is estimated at about 10% from a gate count perspective, 5% in total area overhead.