Punctuation preferences | |
Character | Use |
! | symbol |
# | symbol |
$ | symbol |
% | symbol |
& | symbol |
^ | symbol |
_ | symbol |
` | symbol |
* | symbol |
? | symbol |
@ | symbol |
~ | symbol |
+ | symbol |
- | symbol |
( | token |
) | token |
, | token |
/ | token |
= | token |
[ | token |
\ | token |
] | token |
{ | token |
| | token |
} | token |
. | pseudo |
: | label |
; | comment |
Registers | |
Name | Width |
pc | 12 |
acc | 16 |
ir | 16 |
mar | 12 |
mdr | 16 |
status | 3 |
Register Arrays | ||
Name | Length | Width |
Condition Bits | |||
Name | Register | Bit | Halt |
halt-bit | status | 0 | true |
RAMs | |
Name | Length |
Main | 128 |
Set | ||||
Name | Register | Start Bit | Number of Bits | Value |
Test | ||||||
Name | Register | Start Bit | Number of Bits | Comparison | Value | Omission |
if(acc!=0)skip-1 | acc | 0 | 16 | NE | 0 | 1 |
if(acc>=0)skip-1 | acc | 0 | 16 | GE | 0 | 1 |
Increment | |||
Name | Register | Overflow Bit | Delta |
Inc2-pc | pc | halt-bit | 2 |
Shift | |||||
Name | Source | Destination | Type | Direction | Distance |
Logical | ||||
Name | Type | Source1 | Source2 | Destination |
Arithmetic | ||||||
Name | Type | Source1 | Source2 | Destination | Overflow Bit | Carry Bit |
acc+mdr->acc | ADD | acc | mdr | acc | halt-bit | (none) |
acc-mdr->acc | SUBTRACT | acc | mdr | acc | halt-bit | (none) |
acc*mdr->acc | MULTIPLY | acc | mdr | acc | halt-bit | (none) |
acc/mdr->acc | DIVIDE | acc | mdr | acc | halt-bit | (none) |
Branch | |
Name | Amount |
TransferRtoR | |||||
Name | Source | Src Start Bit | Destination | Dest Start Bit | Number of Bits |
pc->mar | pc | 0 | mar | 0 | 12 |
mar->pc | mar | 0 | pc | 0 | 12 |
ir(4-15)->mar | ir | 4 | mar | 0 | 12 |
mdr->ir | mdr | 0 | ir | 0 | 16 |
mdr->acc | mdr | 0 | acc | 0 | 16 |
acc->mdr | acc | 0 | mdr | 0 | 16 |
ir(4-15)->pc | ir | 4 | pc | 0 | 12 |
TransferRtoA | ||||||||
Name | Source | Src Start Bit | Destination | Dest Start Bit | Number of Bits | Index | Index Start Bit | Index Number of Bits |
TransferAtoR | ||||||||
Name | Source | Src Start Bit | Destination | Dest Start Bit | Number of Bits | Index | Index Start Bit | Index Number of Bits |
Decode | |
Name | IR |
decode-ir | ir |
Set Condition Bit | ||
Name | Bit | Value |
set-halt-bit | halt-bit | 1 |
IO | ||||
Name | Direction | Type | Buffer | Connection |
input-int->acc | input | integer | acc | [Console] |
output-acc->int | output | integer | acc | [Console] |
Memory Access | ||||
Name | Direction | Memory | Data | Address |
Main[mar]->mdr | read | Main | mdr | mar |
mdr->Main[mar] | write | Main | mdr | mar |
EQUs | |
Name | Value |
Instruction Format Fields | ||||||
Name | Type | Number of Bits | Relativity | Signed | Default Value | Values |
addr | required | 12 | absolute | false | 0 | <any> |
unused | ignored | 12 | absolute | true | 0 | <any> |
op | required | 4 | absolute | false | 0 | <any> |
Fetch Sequence |
Microinstructions |
pc->mar Main[mar]->mdr mdr->ir Inc2-pc decode-ir |
Machine Instructions | |||
Name | Opcode (hex) | Format | Microinstructions |
stop | 0 | op unused | set-halt-bit End |
load | 1 | op addr | ir(4-15)->mar Main[mar]->mdr mdr->acc End |
store | 2 | op addr | ir(4-15)->mar acc->mdr mdr->Main[mar] End |
read | 3 | op unused | input-int->acc End |
write | 4 | op unused | output-acc->int End |
add | 5 | op addr | ir(4-15)->mar Main[mar]->mdr acc+mdr->acc End |
subtract | 6 | op addr | ir(4-15)->mar Main[mar]->mdr acc-mdr->acc End |
multiply | 7 | op addr | ir(4-15)->mar Main[mar]->mdr acc*mdr->acc End |
divide | 8 | op addr | ir(4-15)->mar Main[mar]->mdr acc/mdr->acc End |
jump | 9 | op addr | ir(4-15)->pc End |
jmpz | A | op addr | if(acc!=0)skip-1 ir(4-15)->pc End |
jmpn | B | op addr | if(acc>=0)skip-1 ir(4-15)->pc End |